Clock signals can be used to regulate the operation of both digital and analog circuits. Analog-to-digital converters (ADCs) can utilize a clock signal to regulate the performance of conversion functions. FIG. 1 depicts an ADC 20 configured to receive an analog input signal VAnalogIn and a clock input signal VClockIn, and output a digital signal VDigitalOut. Such a converter 20 typically relies on the precision of the duty cycle of the clock signal VClockIn to allot sufficient time for internal amplifiers to settle to steady- or quasi-steady-state conditions before a new conversion cycle begins. When the duty cycle of the clock signal VClockIn is not as expected, for example because of clock jitter in which the rising or falling edge of the clock signal VClockIn is displaced in time from its expected occurrence in response to noise or other undesirable circuit effects, the performance metrics of the ADC 20 can be deleteriously affected.
Circuits requiring a clock signal can utilize a duty cycle stabilizer (DCS) to ensure the precision of the duty cycle of the clock signal. FIG. 2 depicts an embodiment of a circuit 24 including the ADC 20 and a DCS 28. The DCS 28 receives the clock in signal VCLockIn from a clock signal generator or another circuit, and produces a clock out signal VCLockOut, for use by the ADC 20, having a predetermined duty cycle. In this way, the ADC 20 can rely on the precision of the duty cycle to achieve desired performance metrics. Optionally, the DCS 28 can produce a plurality of clock out signals VClockOutA, VClockOutB, . . . VClockOutI having a plurality of different predetermined duty cycles. For example, the clock out signal VClockOut delivered to the ADC 20 may have a precise 50% duty cycle, whereas the other clock out signals VClockOutA, VClockOutB, . . . VClockOutI may have precise duty cycles of 25%, 50%, 75%, etc., or any other desired predetermined duty cycle value.
FIG. 3 depicts one embodiment of a DCS 32 for producing a clock out signal VClockOut having a predetermined duty cycle. The depicted DCS 32 includes an integrator 36, a ramp circuit 40, a Schmidt trigger 44, and an SR latch 48. In operation, a rising edge of the clock in signal VClockIn is received at the set input S of the latch 48, setting the latch 48 and producing a rising edge of the clock out signal VClockOut. The clock out signal VClockOut feeds back to the integrator 36 and the ramp circuit 40. The integrator 36 generates a substantially DC output control signal having a level indicative of the duty cycle of the clock out signal VClockOut. At the same time, the output of the ramp circuit 40 is reset by the rising edge of the clock out signal VClockOut and begins to ramp up at a rate set by the value of the output of the integrator 36. At a certain point the rising output value of the ramp circuit 40 triggers the Schmidt trigger 44. The ramp circuit 40 and Schmidt trigger 44 thus effectively act as variable delay cell that produces an output pulse to the reset input R of the SR latch 48 that resets the latch 48, producing a falling edge of the clock out signal VClockOut. The ramp circuit 40 is configured such that when the clock out signal VClockOut has the desired predetermined duty cycle, it generates an output signal that ramps at a correct rate to produce the desired duty cycle. The negative feedback action of the depicted DCS 32 regulates the clock out signal VClockOut to maintain the predetermined duty cycle. When the duty cycle of the clock out signal VClockOut is greater or less than the predetermined value, the integrator 36 produces an output signal to the ramp circuit 40 that increases or decreases the rate at which the ramp circuit 40 ramps, triggering the Schmidt trigger 44 sooner or later to producing a reset pulse to the SR latch 48 sooner or later, thereby adjusting the falling edge of the clock out signal VClockOut in a manner to return it to the predetermined duty cycle.
One problem with the DCS 32 depicted in FIG. 3 is that the integrator 36 is essentially a continuous-time circuit, integrating the clock out signal VClockOut continuously. However, in duty cycle stabilization, the primary concern is often the placement of the edges of the clock signal. Thus, the integrator 36, in integrating the entire signal, time-wise, is integrating many moments of little concern, and is thus unnecessarily susceptible to error arising during these moments of little concern. For example, noise can generally decrease the operating precision of circuits, and this effect potentially has greater impact on an integrator 36 operating continuously than a circuit which only operates during the periods of import, i.e., the edge-transition periods of the clock out signal VClockOut. Thus, the continuous-time nature of the DCS circuit 32 can limit its performance metrics.